The advent of new, faster microprocessors, such as Intel's i486 brand microprocessor, have not immediately resulted in improved computer performance. This is because the performance enhancement from the faster microprocessor execution time is limited by the percentage of the time the microprocessor is allowed to complete a cycle without incurring many waitstates. Prior main memories used in conjunction with microprocessors have been a cause of this performance limitation. Pipelining increases microprocessor throughput, but main memory design constraints require latching of main memory addresses, write enable signals, etc. This additional signal setup contributes to increased main memory access times and hold timing requirements. Signal skew also contributes to increased main memory access time. If the access time for the main memory is greater than the microprocessor minimum cycle duration then wait states must be added to microprocessors memory accesses, degrading system performance.
Arrays of dynamic random access memories (DRAMS) are commonly used as main memories in computer systems. The demanding set-up and hold-times associated with DRAMs frequently prevents computer systems from realizing the greatest performance possible given the chosen microprocessor. For example, Intel's i486 microprocessor is capable of performing four consecutive 32-bit reads; however, prior DRAM main memories could not support such data bursting without complex interface circuitry.
A disadvantage of the prior art is that individual DRAM access strobes and address signals must be buffered to ensure signal integrity.
A disadvantage of the prior art is that control logic is necessary to select and control several DRAM partitions in a large DRAM array.
Another disadvantage of the prior art is that skew between signals must be tightly controlled to ensure reliable operation at or near DRAM minimum access times. Tight control of signal skew required expensive high speed logic devices or expensive application specific integrated circuits.
Another disadvantage of prior DRAM main memories is that address signals may not change prior to meeting DRAM address hold times.
Yet another disadvantage of prior DRAM main memories is that as DRAM arrays increase in size the number of signals required to interface with the array become prohibitive. This is because separate address lines, RAS lines, CAS lines, write enable lines and data lines are typically needed for each partition within the array.